The present invention relates to an analog switch device using MOS transistors.
An analog switch device transmits an analog input signal when set to ON, while the device does not transmit the analog input signal when set to OFF. The analog switch device of this type preferably produces a voltage signal which is equal to or linearly proportional to the input signal. For this purpose, an input-output resistance of the analog switch device must be kept constant. However, if MOS transistors are used in the analog switch device, an output voltage of the analog switch becomes non-linear in relation to the input voltage. This is because the MOS transistors have a source-substrate bias effect, causing the resistance of the MOS transistors to become non-linear. An analog switch device is proposed which utilizes this resistance characteristic of CMOS transistors. However, in the analog switch device using the CMOS transistors, an impurity concentration of a substrate region of an n-channel MOS transistor is generally higher than that of a substrate region of a p-channel MOS transistor. As a result, the source-substrate bias effect of the n-channel MOS transistor is greater than that of the p-channel MOS transistor. A change in the resistance of the n-channel MOS transistor which is obtained in response to the input analog signal is greater than that of the p-channel MOS transistor, so that significant distortion of an output analog signal occurs.
U.S. Pat. No. 3,720,848, for example, discloses a means for solving this problem. In an analog switch disclosed in the above patent specification, a means is provided for selectively forming a short circuit between a source region and one substrate region of the n- and p-channel transistors when either the n- or p-channel transistor is rendered conductive. However, in this device, since the source region and the substrate region are shortcircuited, the potential at the drain region becomes lower than that of the substrate region. Note that a parasitic npn bipolar transistor is formed having a drain region of the n-channel transistor as an emitter, a substrate region of the n-channel transistor as a base, and a substrate region of the p-channel transistor as a collector. If the potential of the emitter is lower than that of the base as described above, the emitterbase path is forward biased, resulting in flow of a wasteful current through the bipolar transistor.